This relates to a frequency divider and, more particularly, to one which can be switched so as to divide an input signal by one of a plurality of different values. The divider has the further advantage that its output signal has approximately a 50 percent duty cycle and that switching between one divisor and another takes place only upon completion of a division cycle.
As is well known, data is often transmitted over a communication line in the form of pulses of certain frequencies. In a communication system using frequency shift keying (FSK), one of two DC levels that represents digital data is converted by a modem to an AC signal having a first frequency; and the other level of the DC signal is converted to an AC signal having a second frequency. It is conventional in the art to refer to the lower of these DC levels and corresponding AC frequency as a SPACE or "0" and to the higher DC level and the corresponding AC frequency as a MARK or "1".
One method for obtaining the two frequency signals representative of MARK and SPACE is to divide down the output of a suitable oscillator by different amounts. For example, the output of a 17.5 MHz oscillator can be divided by 7 to produce a 1.5 MHz signal representative of a MARK; and it can be divided by 5 to produce a 3.5 MHz signal representative of a SPACE.
There are several constraints, however, on the use of such division techniques to generate the different frequency levels which might be used in data communication. First, to simplify post modulation filtering of the output signal it is desirable that the output of the frequency divider have approximately a 50 percent duty cycle in order to minimize any DC component in the output signal. Second, to eliminate telegraph switching distortions, it is desirable to permit changes in the magnitude of the frequency divisor only when the divisor has completed a division. Third, it is desirable to minimize the number of elements required to form the desired frequency divider.